{"id":785,"date":"2022-12-19T12:56:00","date_gmt":"2022-12-19T12:56:00","guid":{"rendered":"http:\/\/imalogic.com\/blog\/?p=785"},"modified":"2022-12-19T19:55:45","modified_gmt":"2022-12-19T19:55:45","slug":"intrinsic-functions-sse-avx","status":"publish","type":"post","link":"https:\/\/imalogic.com\/blog\/2022\/12\/19\/intrinsic-functions-sse-avx\/","title":{"rendered":"Intrinsic functions, SSE, AVX…"},"content":{"rendered":"\n

Normally, \u201cintrinsics\u201d refers to functions that are built-in \u2014 i.e. most standard library functions that the compiler can\/will generate inline instead of calling an actual function in the library. For example, a call like:\u00a0memset(array1, 10, 0)<\/code>\u00a0could be compiled for an x86 as something like:<\/p>\n\n\n\n

 mov ecx, 10\n xor eax, eax\n mov edi, offset FLAT:array1\n rep stosb<\/code><\/pre>\n\n\n\n
Intrinsics like this are purely an optimization. \u201cNeeding\u201d intrinsics would most likely be a situation where the compiler supports intrinsics that let you generate code that the compiler can\u2019t (or usually won\u2019t) generate directly. For an obvious example, quite a few compilers for x86 have \u201cMMX Intrinsics\u201d that let you use \u201cfunctions\u201d that are really just direct representations of MMX instructions.<\/p>\n\n\n\n
Streaming SIMD Extensions<\/strong>\u00a0(SSE<\/strong>) is a single instruction, multiple data (SIMD<\/a>)\u00a0instruction set<\/a>\u00a0extension to the\u00a0x86<\/a>\u00a0architecture, designed by\u00a0Intel<\/a>\u00a0and introduced in 1999 in their\u00a0Pentium III<\/a>\u00a0series of\u00a0Central processing units<\/a>\u00a0(CPUs) shortly after the appearance of\u00a0Advanced Micro Devices<\/a>\u00a0(AMD\u2019s)\u00a03DNow!<\/a>. SSE contains 70 new instructions, most of which work on\u00a0single precision<\/a>\u00a0floating point<\/a>\u00a0data. SIMD instructions can greatly increase performance when exactly the same operations are to be performed on multiple data objects. Typical applications are\u00a0digital signal processing<\/a>\u00a0and\u00a0graphics processing<\/a>.<\/p>\n\n\n\n
Intel\u2019s first\u00a0IA-32<\/a>\u00a0SIMD effort was the\u00a0MMX<\/a>\u00a0instruction set. MMX had two main problems: it re-used existing\u00a0x87<\/a>\u00a0floating point registers making the CPUs unable to work on both floating point and SIMD data at the same time, and it only worked on\u00a0integers<\/a>. SSE floating point instructions operate on a new independent register set, the XMM registers, and adds a few integer instructions that work on MMX registers.<\/p>\n\n\n\n
SSE was subsequently expanded by Intel to\u00a0SSE2<\/a>,\u00a0SSE3<\/a>,\u00a0SSSE3<\/a>, and\u00a0SSE4<\/a>. Because it supports floating point math, it had wider applications than MMX and became more popular. The addition of integer support in SSE2 made MMX a largely\u00a0redundant code<\/a>, though further performance increases can be attained in some situations[when?<\/a><\/em>]<\/sup>\u00a0by using MMX in parallel with SSE operations.<\/p>\n\n\n\n
SSE originally\u2026<\/h2>\n\n\n\n
SSE originally added eight new 128-bit registers known as\u00a0XMM0<\/code>\u00a0through\u00a0XMM7<\/code>. <\/p>\n\n\n\n
SSE used only a single data type for XMM registers:<\/p>\n\n\n\n